NEWS & EVENTS

Thank you for your interest in Forte and our Cynthesizer SystemC synthesis product.

Unfortunately, registration for DAC has closed but you can still reach us to schedule a meeting by sending email to sales@ForteDS.com or by stopping by Booth #3417 at the show. And, while you are at DAC, we've got some really cool things to see after your Cynthesizer meeting including:

• Caricatures on Monday and Tuesday
• Cocktails at our booth on Tuesday at 4pm!
• The traditional close of DAC with the Bagpipers and drawing for really great prizes including a Galaxy Tab - Wednesday 5:50pm

All of this and more with your friends at Forte, booth #3417.

1. Cynthesizer individual session highlighting the use of SystemC and high-level synthesis in production design environments including: The benefits of using high-level synthesis for hardware design The industry's most complete high-level synthesis feature set and how we differentiate from other HLS tools Why SystemC is critical and why ANSI-C doesn't stack up How to quickly create optimized hardware from high-level descriptions Our new Cynthesizer Ultra and success stories Who should attend: Managers, designers, and other engineers interested in significantly improving their overall design, verification and implementation process.

2. CellMath Designer individual session highlighting the use of RTL datapath optimization and IP in production design environments including: The benefits of using datapath optimization technology in your existing flow How to optimize existing datapath RTL to reduce area, improve power and increase speed A real formal verification flow for complex datapath designs Design creation using Forte's CellMath IP CellMath Designer success stories Who should attend: Managers, designers, and other engineers interested in quickly improving results on existing RTL designs and improving their formal verification flow.

3. Tutorial: An Introduction to Behavioral Synthesis with Cynthesizer (Limited seating) Creation and synthesis of an advanced, bus-based system including an ARM AMBA® bus, DMA controllers, accelerators, etc. Synthesizing algorithmic C source code to high-quality RTL Integrating Cynthesizer into existing ASIC and FPGA synthesis flows Utilizing sophisticated memory systems with very simple coding styles Who should attend: Designers looking for more detailed information on high-level synthesis, SystemC and how to quickly improve on their existing design and verification flow.

4. Special session: Designer case study of a USB 2.0 design with High-IP Design Company Phil Tharp will share his experience using Cynthesizer to develop IP for his exciting new high-level IP company, HighIP. The presentation includes actual running hardware and will focus on a high-level design methodology using SystemC and Cynthesizer and will include a summary of results for a real USB 2.0 design with ulpi and plb interfaces. He will further describe design trade-offs, the soft and hard verification approaches, and will discuss how high-level IP will create even faster future development and customization. Phil has over 30 years of development experience and is the designer of a USB core that is used extensively throughout the industry. HighIP Design Company is focused on the development of hardware IP for ASICs through the use of High Level Synthesis. Who should attend: Engineers and managers looking to get more detailed technical information about high-level synthesis, SystemC and Cynthesizer

5. University Session - Wednesday 3:00pm - 4:00pm See the latest in Cynthesizer and CellMath technology, discuss trends in design, and exchange ideas on the future of high-level design and synthesis.

We look forward to seeing you at DAC in San Diego!